Power MOS transistor structure
US4890142A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 1988 |
| Grant date | Dec 26, 1989 |
| Priority date | — |
| Expiry date | Jun 17, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention relates to a structure of parallel power MOS transistors, each of which comprises on a common face of a substrate gate, source and drain contact zones and three levels of the connection layers. The first level of connection layers (20) establishes a contact with all the gates and a connection between each gate and the adjacent gates. A second level of the connection layers establishes a contact with all the source regions (22) and drain regions (23) and a connection between each source (or drain) region and the adjacent source (or drain) regions, and has apertures insulating each drain (or source) contact. A third continuous level of the connection layer level (25) establishes a contact with all the drain (or source) regions of the second level of the connection layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.