Dual-tracking phase-locked loop
US4890305A · kind A · utility
13Cited by
7References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 12, 1988 |
| Grant date | Dec 26, 1989 |
| Priority date | — |
| Expiry date | Feb 12, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A dual-tracking phase-locked loop circuit is provided for moving with minimum disruption from conventional PLL operation to processor-controlled tracking of another closely related clock. In addition to conventional PLL components the circuit comprises a processor-controlled up/down counter which may operate alternatively as a link in the loop or as providing the base-line frequency determining value at the time of transition from PLL to processor-controlled tracking operation, thereby ensuring none disruptive transition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.