Multimode expanded memory space addressing system using independently generated DMA channel selection and DMA page address signals
US4891752A · kind A · utility
18Cited by
20References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 3, 1987 |
| Grant date | Jan 2, 1990 |
| Priority date | — |
| Expiry date | Mar 3, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/206
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes a computer address modification system that is advantageously coupled in a bus network to selectively translate memory address data in 16K blocks and provide DMA page addresses which may match the 16K memory address blocks. The modification system includes a mapping RAM selectively providing translated addresses to enable addresses in a 1 megabyte address space to be selectively mapped to a 16 megabyte extended address space. The modification system also includes a page register storing for each addressable 16K block of data for each DMA channel a page address within the extended address space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.