Register scorboarding on a microprocessor chip
US4891753A · kind A · utility
51Cited by
8References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 26, 1986 |
| Grant date | Jan 2, 1990 |
| Priority date | — |
| Expiry date | Nov 26, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3836
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
When a load instruction is encountered, a read operation is sent to the bus control logic, the register is marked as busy, and execution proceeds to the next instruction. When an instruction is executed, it proceeds providing that its source and destination registers are not marked busy; otherwise the instruction is retried. When data are returned as the result of a read operation, the destination register(s) are marked as not busy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.