Divisional operation system for obtaining a quotient by repeated subtraction and shift operations
US4891780A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 11, 1988 |
| Grant date | Jan 2, 1990 |
| Priority date | — |
| Expiry date | Mar 11, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5352
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A divisional operation is performed by the invention, using three registers. The higher order digits or figures of dividend are given to the first register and the lower order digits or figures thereof are given to the second register. In addition, a divisor is given to the third register. Subtraction is performed between the content of the first register and the content of the third register. On the basis of the sign of the result, the quotient is determined. Every time subtraction is performed, a shift operation is conducted in the first and second registers. The quotient is stored in the second register from the least significant bit thereof. In such a shift operation, data of 1 bit is transferred from the most significant bit of the second register to the least significant bit of the first register. Where the data of 1 bit thus transferred represents "1" when the operation is completed, it is detected that division is in an overflow state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.