Modulo arithmetic processor chip
US4891781A · kind A · utility
32Cited by
22References
44Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 22, 1988 |
| Grant date | Jan 2, 1990 |
| Priority date | — |
| Expiry date | Dec 22, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3816
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides for a processor chip for computing addition, multiplication, and exponentiation in a Galois Field of integers modulo a prime number p, GF(p). The invention includes twelve registers for storing n-bit integers, a full adder for shifting left and adding data stored in two of the registers. A feedback register is included for storing a n-bit number and means for generating a feedback number is provided, wherein the feedback number is generated from a prime number, p. Also included are modulo means for reducing data bits stored in the registers modulo a prime number p.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.