Loadable ripple counter
US4891827A · kind A · utility
11Cited by
4References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 7, 1988 |
| Grant date | Jan 2, 1990 |
| Priority date | — |
| Expiry date | Mar 7, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/665
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A loadable N-bit ripple counter having N bit subcircuits that each inlude a flip-flop and a bit loading element. The flip-flop output is controllable to a known state when a flip-flop control signal is asserted. The bit loading element is connected to receive the flip-flop output and a bit input of a multibit number being loaded and to provide a bit output of the counter, the bit output being controlled by the states of the flip-flop output and the bit input, and, except for the most significant bit, serving as a clock for the next more significant bit subcircuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.