Method and circuit for providing adjustable control of short circuit current through a semiconductor device
US4893211A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 1985 |
| Grant date | Jan 9, 1990 |
| Priority date | — |
| Expiry date | Apr 1, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/0822
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for limiting short circuit current flow in a Field Effect Transistor (FET) to limit the power dissipated therein includes sensing a rise in the drain-to-source voltage of the transistor and clamping the gate-to-source voltage to a predetermined adjustable value thereby reducing the magnitude of the short circuit current flow to within the safe operating characteristics of the device. A comparator switch circuit is responsive to the drain-to-source voltage of the FET exceeding a reference voltage value for clamping the gate-to-source voltage to a predetermined reduced voltage. A trimmable resistive network is connected between the gate and the source electrode of the transistor for adjusting the gate to source clamped voltage potential to compensate for variations in transistor transconductances from one transistor to the next that they may be used in conjunction with the electronic circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.