Patent · US Expired

Digital decimation filter

US4893264A · kind A · utility

7Cited by

3References

3Claims

0Family size

Assignee

Siemens Aktiengesellschaft · DE

Inventors

Tobias Noll · Neckartailfingen, DE
Stefan Meier · Neubiberg, DE

Key dates

Filing date	Jul 25, 1988
Grant date	Jan 9, 1990
Priority date	—
Expiry date	Jul 25, 2008

Classification

Technology area (CPC H)Electricity
CPC primaryH03H2017/0692
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A digital decimation filter which includes a multiplexer which receives signal values x.sub.i at a sampling rate of 1/T and where output signals which have half the sampling rate are supplied to two outputs. Separate bit associated circuits BP1 and BP2 are connected to the outputs for each significant figure of the p-place binary filter coefficients c6 through c1 and each of the bit associated circuits include partial products stages Mc6.sub.0 . . . Mc1.sub.0, Mc6.sub.1 . . . Mc1.sub.1 for all of the filter coefficient bits and the bit associated circuits also contain adder-register iterative circuits including delay elements and the output of the iterative circuit of the most significant bit plane BP2 is the output of the filter.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.