Circuit and method for accumulating partial products of a single, double or mixed precision multiplication
US4893268A · kind A · utility
32Cited by
4References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 15, 1988 |
| Grant date | Jan 9, 1990 |
| Priority date | — |
| Expiry date | Apr 15, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3816
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for use in conjunction with a multiplier receives a portion of completed product bits and a portion of sum and carry bits which, when accumulated, provide a complete output product operand. The circuit is adaptable for use with input operands having single or double precision data formats. The accumulation time required depends upon which data format mode the circuit is operating in.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.