Semiconductor memory device including precharge/equalization circuitry for the complementary data lines
US4893278A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 10, 1987 |
| Grant date | Jan 9, 1990 |
| Priority date | — |
| Expiry date | Jun 10, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The semiconductor memory has a memory array comprising word lines, complementary data lines orthogonal to the word lines, and static memory cells disposed at intersections of the word lines and between a complementary pair of data lines in a grid-like memory matrix arrangement of rows and columns. There is also included a plurality of precharge circuits for selectively setting one of two adjacent complementary data line pairs to a first voltage and the other one of the two complementary data line pairs to a second voltage, different than the first voltage, and further including equalization circuitry, thereby establishing a short-circuit between the complementary data lines of each pair of complementary data lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.