CMOS implementation of a built-in self test input generator (BISTIG)
US4893311A · kind A · utility
26Cited by
4References
3Claims
0Family size
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Key dates
| Filing date | Apr 25, 1988 |
| Grant date | Jan 9, 1990 |
| Priority date | — |
| Expiry date | Apr 25, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318516
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A CMOS implementation of a Built In Self Test Input Generator (BISTIG) for testing embedded PLA structures. The BISTIG tests for all stuck at faults, cross-point faults and bridging faults, by asserting exactly one input row and exactly one product term of the PLA under test at a time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.