Gate control circuit for a switching power MOS transistor
US4894568A · kind A · utility
12Cited by
5References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 2, 1989 |
| Grant date | Jan 16, 1990 |
| Priority date | — |
| Expiry date | Feb 2, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/6877
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A gate control circuit for a power MOS transistor (1), the first main electrode (D) of which is connected to a high voltage (V.sub.CC) through a load (L), the second main electrode (S) of which is grounded and the gate (G) of which is connected, during the switching ON period, to a low voltage source (V.sub.DD), comprises a switch (S1) for connecting at the switching ON of the power MOS transistor its first main electrode to its gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.