LSI chip with scanning circuitry for generating reversals along activated logical paths
US4894830A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 19, 1988 |
| Grant date | Jan 16, 1990 |
| Priority date | — |
| Expiry date | Jan 19, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/27
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A plurality of first flip-flop circuits are provided having outputs connected respectively to inputs of a logic circuit. During a test mode, scan data is first loaded into the flip-flop circuits to activate desired logical paths in the logic circuit and subsequently a pulse is scanned across the first flip-flop circuits to cause successive reversals to occur in the stored scan data. As a result, test signals can propagate through the activated logical paths. Connected to the outputs of the logic circuit are a plurality of second flip-flop circuits which are configured into a linear feedback shift register during the test mode to enable a test circuit to observe its serial output to determine the dynamic performance of the logic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.