FET overtemperature protection circuit
US4896245A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 13, 1989 |
| Grant date | Jan 23, 1990 |
| Priority date | — |
| Expiry date | Mar 13, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2017/0806
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A first signal (V.sub.1) related to FET drain to source voltage and a second signal (V.sub.2) related to FET source current are compared and the FET (11) is turned off when the first signal exceeds the second signal by a predetermined amount. This corresponds to turning the FET off whe the drain to source on resistance of the FET exceeds a FET on resistance value corresponding to a maximum allowable FET die temperature. Thus the FET is turned off for excessive due temperatures to prevent damage to the FET. A start-up circuit (41, 42) is provided to insure proper initial turning on of the FET, and a short circuit protection circuit (30) is provided for turning the FET off it the source current exceeds some maximum current limit. Accurate, effective monitoring of the FET die temperature is provided without the use of an additional temperature sensing element provided adjacent the FET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.