Linking interface system using plural controllable bidirectional bus ports for intercommunication amoung split-bus intracommunication subsystems
US4896256A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 14, 1986 |
| Grant date | Jan 23, 1990 |
| Priority date | — |
| Expiry date | May 14, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N7/152
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A plurality of data processor components are distributed along a plurality of intracommunication bus systems, each intracommunication bus system having an address bus and each being assigned a unique set of addresses, with at least one of the components associated with each of the intracommunication bus systems including an address signal generator for generating address signals over the address bus of the associated intracommunication bus system. An intercommunication bus system is utilized in combination with a plurality of link interface units, with each link interface unit connected between the intercommunication bus system and a corresponding one of the intracommunicaton bus systems, for carrying out communication of information over the intercommunication bus system between first and second of the intracommunication bus systems, in response to the address signals on the address bus of the corresponding one of the intercommunication bus systems. A related method is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.