Semiconductor memory device with row and column word lines and row and column bit lines
US4896294A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 1988 |
| Grant date | Jan 23, 1990 |
| Priority date | — |
| Expiry date | Oct 25, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/408
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell contains a first MOS transistor, a second MOS transistor, and a capacitor, which are connected at the first ends to one another. A word line for a first cell series, is connected to the gates of first MOS transistors in the memory cells arrayed in a row. A word line for a second cell series, is connected to the gates of second MOS transistors arrayed in a column. A bit line for the first cell series, is connected to the second ends of the first MOS transistors in the row. A bit line for the second cell series, is connected to the second ends of the second MOS transistors in the column. A selection circuit selects the first cell series or the second cell series, according to an external input signal for cell series selection. According to the semiconductor memory deivce, one of the first and second cell array series of the memory cell array can be accessed according to a logic level of the array series select signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.