Circuit arrangement for processing sampled analogue electrical signals
US4897596A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1988 |
| Grant date | Jan 30, 1990 |
| Priority date | — |
| Expiry date | Dec 16, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit arrangement for processing sampled analog electric signals includes a low voltage cascode current mirror circuit arrangement having an input branch comprising first and second FETs (T1,T3) and an output branch comprising third and fourth FETs (T2,T4). In order to provide the correct bias potential of V.sub.t +2V.sub.on at the gate electrodes of the second and fourth FETs (T3,T4) a second output branch comprising two further FETs (T5,T6) and a further current mirror circuit comprising two other FETs (T7,T8) pass a current through a diode connected FET (T9) so that it produces a voltage V.sub.t +V.sub.on. If this current is equal to the input current, then the diode connected FET (T9) is constructed to have a gate width to length ratio of one quarter of that of the cascode connected transistors (T3,T4). The current mirror circuit may be incorporated into current scaling and current memory circuits for signal current manipulation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.