Complementary voltage interpolation circuit with transmission delay compensation
US4897656A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 1987 |
| Grant date | Jan 30, 1990 |
| Priority date | — |
| Expiry date | Dec 2, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/141
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention centers around a system for interpolating between multiple pairs of complementary main signals to generate further pairs of complementary signals. An input circuit (10) supplies the main signals. The interpolation is a two-step operation. The first step is done with two strings (S and S.sub.N) of impedance elements (R.sub.0 -R.sub.N-1 and R.sub.N0 -R.sub.NN-1). Each pair of main signals is supplied to a corresponding pair of nodes along the strings. Interpolated signals are taken from other pairs of corresponding nodes along the strings. In the second interpolation stage, a delay network (D) formed with additional impedance elements (R.sub.D0 -R.sub.DN-1 and R.sub.DN0 -R.sub.DNN-1) compensates for transmission delays through the impedance elements that make up the strings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.