Hierarchical arbitration system
US4897833A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 1987 |
| Grant date | Jan 30, 1990 |
| Priority date | — |
| Expiry date | Oct 16, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17337
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hierarchical arbitration system is especially useful in a computer interconnect coupler having a set of junctors which are assigned to channel transmitters and channel receivers for the routing of messages from the channel receivers to the channel transmitters. When a message is received by a channel receiver, the channel receiver stores the beginning portion of the message in a first-in-first-out buffer, and sends a route message request to central switch logic. If the destination transmitter or receiver is busy, the central logic places the message request on a destination queue and returns a signal to the requesting source transmitter to turn on a flow control signal which is transmitted back to the data processing device having originated the message. To permit incremental expansion of the coupler to accommodate an increased number of channels, additional channel interface boards may be added and a hierarchical rotating priority scheme enables the additional channels to have equal priority with the previously existing channels without requiring reprogramming. A ring channel arbitrator is provided for selecting a particular one of the boards during each cycle when a service re…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.