Bit line precharge in a bimos ram
US4899317A · kind A · utility
19Cited by
6References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 1, 1988 |
| Grant date | Feb 6, 1990 |
| Priority date | — |
| Expiry date | Feb 1, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a static random access memory in which the array is comprised of MOS transistors and at least some of the peripheral circuits are comprised of bipolar transistors, the bit lines and data lines are precharged to a base to emitter voltage drop (i.e. one Vbe) below the positive power supply voltage. This increases cell stability. Additionally, Vbe varies comparatively little over process. Additionally, precharging the bit lines and data lines to a Vbe below the positive power supply voltage allows for the use of a high speed bipolar differential amplifier in its optimum operating range as the first stage sense amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.