Process for making polysilicon field plate with improved suppression of parasitic transistors
US4900693A · kind A · utility
13Cited by
9References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 21, 1987 |
| Grant date | Feb 13, 1990 |
| Priority date | — |
| Expiry date | Dec 21, 2007 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/953
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming silicon integrated circuits offers radiation resistance together with a high degree of planarity, including a thin field oxide together with a set of conductive plates over the field region combine to suppress the formation of parasitic transistors. In one embodiment, a silicon substrate is etched to form trenches and is then covered with a thin barrier layer, (410) of high quality thermal oxide. A polysilicon layer (423) is next conformally deposited and planarized until the barrier layer (410) is exposed, followed by an oxidation step for isolation or gate oxide formation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.