Gated architecture for computer vision machine
US4901360A · kind A · utility
28Cited by
10References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 23, 1987 |
| Grant date | Feb 13, 1990 |
| Priority date | — |
| Expiry date | Oct 23, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer architecture 10 for performing iconic and symbolic operations on image data is disclosed. Three levels of processing elements (CAAPP, ICP, GPPA) are disclosed. The processing elements in the lowest level (CAAPP) are provided with a plurality of controllable gates (N, S, E, W, H, V, NW, NE) that are used to selectively connect together processing elements in that level. In such manner, certain algorithms such as the minimum spanning tree algorithm can be efficiently performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.