Process for making a bipolar integrated circuit
US4902633A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 9, 1988 |
| Grant date | Feb 20, 1990 |
| Priority date | — |
| Expiry date | May 9, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bipolar integrated circuit requiring less silicon area is provided by the use of a three layer epitaxy on top of a substrate. The first epitaxial layer is of the same conductivity type as the substrate and adds additional height to the substrate surrounding the buried layer. The buried layer serves as a collector and it is surrounded by an isolation area. The top two epitaxial layers are of a conductivity type opposite to that of the substrate with the upper most epitaxial layer having a higher dopant density than does the middle epitaxial layer. A master mask is used to provide self-alignment between the isolation area, a collector plug which makes contact to the buried layer, and a base region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.