DC/DC converter
US4902957A · kind A · utility
20Cited by
7References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 27, 1989 |
| Grant date | Feb 20, 1990 |
| Priority date | — |
| Expiry date | Apr 27, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/156
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A latch (29) is set by a clock (33) to turn on power switch (FET 5). The latch (29) is reset by high voltage comparator (21), by a 50 percent clock delay (35) and by a low-voltage-to-charging-current comparator (19). The voltage at turn-on is compared with a up-ramping reference (15) until it equals an operating reference (17). A temporary delay (pulse circuit 39 and gate 37) is provided before the low voltage comparison can be effective. The delay prevents response to parasitic effects across the power switch (5). Excess drive is prevented resulting from low output currents and malfunctions, and at turn-on.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.