Chip carrier with interconnects on lid
US4903120A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 1985 |
| Grant date | Feb 20, 1990 |
| Priority date | — |
| Expiry date | Nov 22, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip carrier with multiple through hole vias in its hermetic sealing lid. One or more chips is mounted on the inner surface of that lid. The lid contains multiple through vias, and the semiconductor chip on the inner surface of the lid is bonded to the vias in the lid by TAB strips or (optionally) by wire bonds. The vias in the lid connect these leads through to contacts on the outer surface of the package. These contacts can than be connected to (using interconnect structures such as TAB strips, or printed wiring boards, or discretionary wiring), to provide circuit interconnection. Preferably low-power-dissipation chips are mounted on the inner surface of the lid in this fashion, with higher-power-dissipation chips mounted on the bottom surface of the chip cavity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.