Method of increasing the speed of test program execution for testing electrical characteristics of integrated circuits
US4903199A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 1988 |
| Grant date | Feb 20, 1990 |
| Priority date | — |
| Expiry date | Apr 19, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/865
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed is a method which speeds up interpretive test program code execution and allows rapid changes to the test code. The tester utilized with the present invention uses the interpretive language TPL (Test Program Language) for device test programs. The present invention uses the first execution of a statement in an interpreted environment to build a table of address value pairs corresponding to the values computed by the statement. It then changes the pseudo code of the statement to use a short assembly language routine to write the values in the table fo their appropriate addresses, using the memory mapped features of the test head hardware. This is done by translating each TPL line into pseudo code as it is loaded. The first time a line of code is executed, it builds a table which contains all the values computed and the addresses to which they are written. The next time the statement is executed, the verb pointer points to the turbo software which is executed rather than the TPL statement. Since the test head hardware is memory mapped, no distinction needs to be made between data being saved by the software and data being written to the test head. All error checking and cal…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.