Frame buffer architecture capable of accessing a pixel aligned M by N array of pixels on the screen of an attached monitor
US4903217A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 1987 |
| Grant date | Feb 20, 1990 |
| Priority date | — |
| Expiry date | Feb 12, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/123
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A frame buffer memory organization which is capable of accessing a pixel aligned M by N array of contiguous pixels on the screen from a frame buffer memory constructed of an M by N array of memory chips by driving a common address bus to all the memory chips, and by driving N RAS wires horizontally across the memory chip array and M CAS wires vertically down the memory chip array. The writing of individual pixels in this array is enabled by energizing the write enable pins to each memory chip directly. The data wires in the memory organization are tied together such that M horizontal pixels in a single row can be read or written simultaneously. Additionally, all M and N pixels may be written simultaneously if the data in all vertical columns is the same. The frame buffer includes a selectively energizable plane mask for disabling desired planes of accessed pixels. By sequentially controlling the output enables to the different rows of the addressed M by N array, the frame buffer can provide rapid access to N-1 rows after normally accessing the first one. The described architecture will work equally well for M by N other array organizations with a different size (e.g., 8 by 8, 3 by …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.