Transposition memory for a data processing circuit
US4903231A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 1, 1988 |
| Grant date | Feb 20, 1990 |
| Priority date | — |
| Expiry date | Jul 1, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory of n.times.n digital data, is adapted to receive the n.times.n data from a matrix block in line order after line and to output the data in column after column order. Such a memory is particularly useful for circuits carrying out digital transformations such as cosinus transformations wherein one must first carry out a line transformation then a column summation. The memory is constituted by a network of n.times.n registers REG(i,j) and of n.times.n multiplexers MUX(i,j); the registers are operated at a period T and the multiplexers at a period n.times.T. The connections between the memory inputs and outputs and the register network are alternatively connected at the period n.times.T in order that in a first phase the data are introduced and "horizontally" shifted inside the network and that in a second phase the data are introduced and "vertically" shifted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.