Time-division multiplex switching network
US4903259A · kind A · utility
9Cited by
2References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 21, 1988 |
| Grant date | Feb 20, 1990 |
| Priority date | — |
| Expiry date | Jul 21, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q11/08
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A switching network is constituted by a plurality of time switches which are arranged in a matrix and at cross points between a plurality of input buses and a plurality of output buses, on which frame synchronization signals are multiplexed. Each time switch includes a data memory in which data on the input bus is written in synchronism with the frame synchronization signal included in the input bus, and from which data is read out under the address control of a control memory in synchronization with the frame synchronization signal included in the output bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.