Semiconductor memory device with staggered sense amplifiers
US4903344A · kind A · utility
106Cited by
4References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 6, 1988 |
| Grant date | Feb 20, 1990 |
| Priority date | — |
| Expiry date | Jul 6, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor memory device of an open bit line configuration including a plurality of memory cells arranged in rows and columns, bit lines for adjacent columns are offset by about half their length in the column direction, and each bit line is terminated so as not to overlap, in the vertical direction, the sense amplifier of the bit line for the next column.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.