Array processor and control method thereof
US4905143A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 1988 |
| Grant date | Feb 27, 1990 |
| Priority date | — |
| Expiry date | Jun 14, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8023
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array processor comprising multiplexers, plural processing elements connected through the multiplexers in the form of a ring and a control unit for controlling the multiplexers and the processing elements. Each of the processing elements is connected to an input vector data bus via the multiplexer and directly to an I/O data bus, so that two types of input vector data are inputted to the processing element simultaneously. Flags indicating a position of respective vector data are added to each one of input vector data, series composed of a combination of plural types of input vector data series. The processing element judges a processing status of the processing element to control a selection of the input vector data bus or the transfer path, data transfer between the processing elements, or data input/output to/from the I/O bus, so that the overall array processor executes autonomous control of all the combinations of the vector data of the two types of input vector data series. The array processor realizes parallel processing of pattern matching computation based upon dynamic time warping with a high efficiency and thus realizes a highefficiency utilization of hardware resource…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.