Circuit arrangement for designational reading of information of a bit group oriented, continuous information stream at an
US4905236A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 1988 |
| Grant date | Feb 27, 1990 |
| Priority date | — |
| Expiry date | Jul 13, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q11/0428
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The reading times for a designational reading of information communicated via an ISDN-oriented interface are formed for a recording device and transmitted thereto with the assistance of a circuit arrangement, being formed from bit clock signals and bit group clock signals, which define the boundaries of the bit groups comprising 32 bits, that are present in an ISDN-oriented interface. The reading times present in the form of bit clock pulses inform the recording device of the times at which the information are to be read and subsequently stored. The circuit arrangement contains a shift register that is formed by a plurality of registers corresponding in number to the plurality of bits of a bit group, a reset device that is realized, for example, by an inverter and a switch, and also contains an AND gate and a plurality of switch devices whose setting determines which information are, respectively, bits of a bit group are to be read and stored.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.