Synchronous programmable two-stage serial/parallel counter
US4905262A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 28, 1988 |
| Grant date | Feb 27, 1990 |
| Priority date | — |
| Expiry date | Jul 28, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/665
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A synchronous programmable binary counter has a parallel section and a serial section, with the length (in bits) of the serial section being the same as the modulus of the parallel section. The parallel section counts on system clocks and produces two outputs. A parallel terminal count output is produced each time the parallel section count reaches a programmed value. A frame output is generated every time the parallel section reaches its maximum count and starts counting again. The serial counter section decrements its programmed value by one each time it receives a frame signal from the parallel section. This subtraction is accomplished by a half-adder and associated borrow flip-flop. The borrow flip-flop is set by each arrival of the frame signal. Between frame signals, the decremented programmed value is circulated in a shift register as the serial subtraction process is performed. When the serial section completes its countdown, it detects the all zeros condition in its circulating shift register and sets a flip-flop indicating that it has reached its terminal count. The overall counter will complete its count and will generate a terminal count output when the parallel counter…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.