CMOS analog four-quadrant multiplier
US4906873A · kind A · utility
6Cited by
9References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 12, 1989 |
| Grant date | Mar 6, 1990 |
| Priority date | — |
| Expiry date | Jan 12, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/6872
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A four-quadrant analog multiplier circuit provides an output which is proportional to two voltage inputs. The circuit includes a pair of depletion mode transistors having gain constants equal in magnitude and threshold voltages equal in magnitude. The gates of the transistors are coupled in common. One input is applied to the common gates. The other input and its inverse are separately applied to source/drain terminals of the two transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.