Selective multimode/multiconfigurable data acquisition and reduction processor system
US4907229A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 1988 |
| Grant date | Mar 6, 1990 |
| Priority date | — |
| Expiry date | Jun 23, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved high frequency selective multimode/multiconfigurable data acqition and reduction processor (DARP) system for analyzing more than one high frequency multibit sample data word stream (SDWSM) input from a digital data source arrangement being evaluated. As the result of this analysis, one or more sample data words of any SDWSM are accepted, time-tagged and stored for further analysis in evaluating the arrangement. The DARP system is generally made up of a host computer (HC), a plurality of trigger elements (TEs) and an asynchronous time-tag generator. Each TE is generally comprised of a master control board, a plurality of three trigger boards and a TE memory. The DARP system is advantageously provided with a plurality of five primary modes for each TE as well as various secondary modes therefor. Prior to operating any system TE, the operator of the HC normally sets one or more TEs in a setup mode for preselecting various parameters and secondary modes prior to utilizing one or more TEs in one or more primary modes such as for analyzing a SDWSM input. With the TEs being selectable for at least one primary and different secondary modes, one or more TEs may be configured for…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.