Fault tolerant smart card
US4908502A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 8, 1988 |
| Grant date | Mar 13, 1990 |
| Priority date | — |
| Expiry date | Feb 8, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG07B2017/0079
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A fault tolerant smart card is provided having primary functional units including a standard ISO interface, a first microcontroller, a clock, and main memory. Secondary functional units including a secondary microcontroller, secondary memory with bit checking capability and an alternate battery power source are also provided. A microcontroller error detector is connected to both microcontrollers. Should a discrepancy between microcontrollers occur known test patterns are run on the second microcontroller to determine which microcontroller is faulty. A private access port provides alternate access to information stored in the fault tolerant smart card. Registers for funds remaining, error condition and access account are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.