Patent · US Expired

System for printed circuit board testing

US4908576A · kind A · utility

48Cited by
19References
64Claims
0Family size

Inventor

Key dates

Filing dateSep 8, 1987
Grant dateMar 13, 1990
Priority date
Expiry dateSep 8, 2007

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/2806
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

A system is described for connecting a printed circuit board (PCB) under test to a digital analysis unit to permit verification of the functional behavior of the PCB. A bed-of-nails (BON) fixture is employed, allowing access to internal circuit nodes of the PCB. Controlled-impedance wiring, terminated in its characteristic impedance at the test electronics, allows high speed signals to be communicated without degradation from the unit under test (UUT). Excessive dynamic loading of the UUT circuit nodes is avoided by employing isolation resistance at each BON probe. The potentially large number of UUT signals to be monitored is multiplexed down to a smaller number of lines more readily accommodated by the digital analysis unit. The selected signals from the UUT are processed in a wide-band asynchronous manner by the test electronics in such a way that uniform delay of all signals through the multiplexer is achieved. The digital analysis unit is able to monitor the operation of the UUT just as well as if neither the BON nor any intervening electronics were present. The high-speed functional behavior of the PCB itself remains essentially unaffected by the presence of the BON, test ele…

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.