System for controlling access to computer bus having address phase and data phase by prolonging the generation of request signal
US4908749A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 1985 |
| Grant date | Mar 13, 1990 |
| Priority date | — |
| Expiry date | Nov 15, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing system is disclosed which uses a system busy signal on its system bus to help control access to said bus. One or more requesters can generate a request signal when the system busy signal is not asserted. System busy is asserted along with the request signal(s) and remains asserted until all requesters which generated a request signal have gained access to the bus in order of priority. A freeze signal is generated on the system bus during the address phase of an instruction and a wait signal is generated during each data transfer in the data phase of an instruction. The freeze signal may be generated by a memory control unit, a memory module or a requester.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.