Registered outputs for a memory device
US4908796A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 1988 |
| Grant date | Mar 13, 1990 |
| Priority date | — |
| Expiry date | May 24, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Registered output circuitry for a memory device includes a first latch which stores data from a sense amplifier on the rising edge, and outputs it on the falling edge, of the falling edge of an OE signal. This data stored in the latch is provided as output of only y, during the preceding rising edge of the OE signal the CE signal to the memory device was a logical 0 level, and the WE signal was a logical 1 level. Since the falling edge of the OE signal is the beginning of the memory cycle, the data at the output pin of the memory is the data read in the previous read cycle. This latency, however, enables a shortened average cycle time, and also provides registered outputs without the necessity of an external clock signal applied to the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.