Device to detect the functioning of the read system of an EPROM or EEPROM memory cell
US4908799A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 27, 1989 |
| Grant date | Mar 13, 1990 |
| Priority date | — |
| Expiry date | Feb 27, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/143
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electrically programmable read only memory including an inhibiting circuit for preventing operation of the memory if a reading voltage higher than a predetermined level above a standard reading voltage is applied as a reading voltage during a read operation. The inhibiting circuit includes a detection circuit for providing a detection signal in the event that a reading voltage higher than the standard reading voltage is applied to the memory, and a logic circuit connected to an output of the detection circuit and having an output supplied as an inhibiting signal, for example, to inhibit a clock signal within the integrated circuit, upon reception of the detection signal. In a preferred embodiment, the detection circuit includes an enhanced-type transistor connected in series with a depleted transistor serving as a load. The enhanced transistor has a channel ranging between 50 and 100 microns and a channel length ranging from 4 to 6 microns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.