Semiconductor fuse programmable array structure
US4910418A · kind A · utility
43Cited by
9References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 1988 |
| Grant date | Mar 20, 1990 |
| Priority date | — |
| Expiry date | Dec 29, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A programmable array including FET devices arranged in rows and columns is disclosed in which first and second bit lines for cells in adjacent first and second columns are arranged so that a fusible link connecting a cell of a column to its associated bit line crosses the bit line associated with the adjacent column of cells. By doing so, two fuses may now be located in an area which was heretofore occupied by a single fuse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.