Address conversion apparatus
US4910668A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 1987 |
| Grant date | Mar 20, 1990 |
| Priority date | — |
| Expiry date | Sep 24, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/123
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An address conversion apparatus includes a content addressable memory for storing a plurality of logical addresses, and a random access memory for storing a plurality of physical addresses corresponding to the logical addresses. When an input logical address is received, a search is conducted to find the same logical address stored in the memory. When the same logical address is found, the content addressable memory causes the random access memory to output a corresponding physical address. The content addressable memory includes a plurality of logical address storage units. Each unit has a plurality of data bit cells for storing address data and a process identification number cell for storing a process identification number. Thereby, a plurality of logical addresses which correspond to different processes are stored in the single content addressable memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.