Multiplexer diagnostic input patterns
US4910728A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 27, 1988 |
| Grant date | Mar 20, 1990 |
| Priority date | — |
| Expiry date | Jun 27, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/14
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Binary logic states (ONE, ZERO) are presented to the data inputs (24) of a multiplexer in a pattern characterized by a reversal of the binary logic states at input boundaries defined numerically as radix two raised to successive integer exponents. After sequencing the multiplexer address lines (22) to select the inputs to appear at the multiplexer output (25) in a desired sequence, the assembled output word (27) can, because of the pattern presented to the inputs, uniquely identify one of a number of particular address line conditions. Preselected codes are determined that facilitate identification of the conditions by comparing the codes to the output word in a flowchart of program steps (FIG. 4). Each code is associated with a pair of conditions, a first condition with a comparison result of all ONEs and a second with a comparison result of zero.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.