Programmable summing functions for programmable logic devices
US4912345A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 1988 |
| Grant date | Mar 27, 1990 |
| Priority date | — |
| Expiry date | Dec 29, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17712
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device includes a programmable logic array and an output logic macrocell. The output logic macrocell includes a user configurable summing function that has a first logic gate connected to receive a first plurality of product terms, a second logic gate connected to receive a second plurality of product terms and a third logic gate connected to receive the combination of the first plurality of product terms and a controls signal, a fourth logic gate connected to receive the combination of the second plurality of Product Terms and the control signal and a logic circuit connected to receive the output signals from the first, second, third and fourth logic gates and to provide a first logical combination when the control signal is at a first logic state and a second logical combination when the controls signal is at a second logic state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.