Circuit for limiting inrush current during initial turn-on of a clock-derived power supply
US4912619A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 17, 1988 |
| Grant date | Mar 27, 1990 |
| Priority date | — |
| Expiry date | Jun 17, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05B19/054
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A current limiting circuit wherein a first transistor has an input terminal coupled to a power source, an output terminal coupled to a node which supplies current to the rest of the system, and a control terminal coupled to a source of clock pulses for flowing current from the power source into the node in response to the clock pulses. A second transistor has an input terminal coupled to the power source, an output terminal coupled to the node, and a control terminal coupled to the clock supply and to a current control signal circuit for flowing a second current into the node in response to the clock pulses when a prescribed current control signal is applied to the control terminal. The current which flows through the first transistor is significantly less than the current which flows through the second transistor. When the circuit is initially turned on, the small current flowing through the first transistor operates the system until such time as the large current from the second transistor may be added to it.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.