Flexible VLSI on-chip maintenance and test system with unit I/O cell design

US4912709A · kind A · utility

Assignee

• Control Data Corporation · US

Inventors

• Judy L. Teske · Burnsville, US
• Daniel J. Baxter · Stanley Corners, CA
• Don A. Daane · Burnsville, US
• Brian D. Borchers · Wylie, US
• David H. Allen · Rochester, US
• Michael Maas · Schnorbach, DE

Key dates

• Filing date: Oct 23, 1987
• Grant date: Mar 27, 1990
• Expiry date: Oct 23, 2007

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318538
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

This application describes a peripheral cell structure for VLSI chips that requires the use of standard cells having both input and output capability connected to nearly all of the signal carrying pins. The cells function is alterable (to input or output and to where the data input signals originate) by control signals which may originate with a control register. The clock input signal is split into two independent signals to selectively disable the input or output registers, thus allowing the control register to be changed without affecting the contents of the other two registers. An early signal is also provided to prepare for mode changes.