Method of fabricating a heterojunction bipolar transistor
US4914049A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 1989 |
| Grant date | Apr 3, 1990 |
| Priority date | — |
| Expiry date | Oct 16, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/072
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A heterojunction bipolar transistor having a planar surface topology, reduced lateral dimensions and a base electrode aligned to both the emitter and collector electrodes is fabricated by forming sub-collector, collector, base and one or more emitter layers on a substrate. An opening extending to the sub-collector layer is then formed and a first portion of the collector electrode is formed therein so that the sidewalls of the opening are not contacted by the first portion. Dielectric material is then formed between the sidewalls of the opening and the first portion of the collector electrode. A second portion of the collector electrode is then formed on the first portion of the collector electrode along with an emitter electrode so that the second portion of the collector electrode and the emitter electrode are substantially planar. After then exposing the base layer, the self-aligned base electrode is formed between the second portion of the collector electrode and the emitter electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.