Circuit for holding a MOS transistor in a conduction state in a voltage supply outage situation
US4914316A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 1988 |
| Grant date | Apr 3, 1990 |
| Priority date | — |
| Expiry date | Dec 12, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/063
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for holding a MOS power transistor in a conduction state on the occurrence of an outage in the voltage supply, being of a type which comprises a first MOS transistor having its source connected to a line of the voltage supply and its drain connected to the gate of the power transistor, further comprises a diode connected between the drain of the first transistor and the gate of the power transistor, and a second transistor of the MOS type having its gate connected to the gate of the first transistor drain connected to the gate of the power transistor. The circuit prevents the gate capacitance of the power transistor from becoming discharged on a failure of the voltage supply, thus holding that transistor in a conducting state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.