BIMOS level convertor
US4914321A · kind A · utility
2Cited by
9References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 10, 1989 |
| Grant date | Apr 3, 1990 |
| Priority date | — |
| Expiry date | Apr 10, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09448
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A BIMOS lever convertor (10) comprises a differential circuit having a common biasing network (14). A MOS transistor (16) in one portion of the differential circuit receives a MOS level input signal (32) and provides an ECL level output signal (34). The other portion of the differential circuit includes a bipolar transistor (18) that is biased by the MOS transistor (16). The bipolar transistor (18) operates to provide a complementary ECL level output signal (34') so as to provide a single ended MOS to differential ECL interface suitable for integration in an I.C.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.